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pci.h

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00001 /*
00002  * Copyright 1999 Egbert Eich
00003  *
00004  * Permission to use, copy, modify, distribute, and sell this software and its
00005  * documentation for any purpose is hereby granted without fee, provided that
00006  * the above copyright notice appear in all copies and that both that
00007  * copyright notice and this permission notice appear in supporting
00008  * documentation, and that the name of the authors not be used in
00009  * advertising or publicity pertaining to distribution of the software without
00010  * specific, written prior permission.  The authors makes no representations
00011  * about the suitability of this software for any purpose.  It is provided
00012  * "as is" without express or implied warranty.
00013  *
00014  * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
00015  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
00016  * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
00017  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
00018  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
00019  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
00020  * PERFORMANCE OF THIS SOFTWARE.
00021  */
00022 #include "v86bios.h"
00023 
00024 #ifndef V86_PCI_H
00025 #define V86_PCI_H
00026 
00027 typedef union {
00028         struct {
00029                 unsigned int    zero:2;
00030                 unsigned int    reg:6;
00031                 unsigned int    func:3;
00032                 unsigned int    dev:5;
00033                 unsigned int    bus:8;
00034                 unsigned int    reserved:7;
00035                 unsigned int    enable:1;
00036         } pci;
00037         CARD32 l;
00038 } PciSlot;
00039 
00040 typedef struct pciBusRec {
00041         CARD8 primary;
00042         CARD8 secondary;
00043         CARD32 bctl;
00044         PciSlot Slot;
00045         struct pciBusRec *next;
00046         struct pciBusRec *pBus;
00047 } PciBusRec, *PciBusPtr;
00048 
00049 typedef struct pciStructRec {
00050         CARD16 VendorID;
00051         CARD16 DeviceID;
00052         CARD8 Interface;
00053         CARD8 BaseClass;
00054         CARD8 SubClass;
00055         CARD32 RomBase;
00056         CARD32 bus;
00057         CARD8 dev;
00058         CARD8 func;
00059         CARD32 cmd_st;
00060         int active;
00061         PciSlot Slot;
00062         struct pciStructRec *next;
00063         PciBusPtr pBus;
00064 } PciStructRec , *PciStructPtr;
00065 
00066 
00067 extern PciStructPtr CurrentPci;
00068 extern PciStructPtr PciList;
00069 extern PciStructPtr BootBios;
00070 extern int pciMaxBus;
00071 
00072 extern CARD32 findPci(CARD16 slotBX);
00073 extern CARD16 pciSlotBX(PciStructPtr);
00074 PciStructPtr findPciDevice(CARD16 vendorID, CARD16 deviceID, char n);
00075 PciStructPtr findPciClass(CARD8 intf, CARD8 subClass, CARD16 class, char n);
00076 
00077 extern CARD8 PciRead8(int offset, CARD32 slot);
00078 extern CARD16 PciRead16(int offset, CARD32 slot);
00079 extern CARD32 PciRead32(int offset, CARD32 slot);
00080 
00081 extern void PciWrite8(int offset,CARD8 byte, CARD32 slot);
00082 extern void PciWrite16(int offset,CARD16 word, CARD32 slot);
00083 extern void PciWrite32(int offset,CARD32 lg, CARD32 slot);
00084 
00085 extern void scan_pci(int);
00086 extern void pciVideoDisable(void);
00087 extern void pciVideoRestore(void);
00088 extern void EnableCurrent(void);
00089 extern int mapPciRom(PciStructPtr pciP);
00090 extern int cfg1out(CARD16 addr, CARD32 val);
00091 extern int cfg1in(CARD16 addr, CARD32 *val);
00092 extern void list_pci(void);
00093 extern PciStructPtr findPciByIDs(int bus, int dev, int func);
00094 
00095 #define PCI_MODE2_ENABLE_REG  0xCF8
00096 #define PCI_MODE2_FORWARD_REG  0xCFA
00097 #define PCI_MODE1_ADDRESS_REG  0xCF8
00098 #define PCI_MODE1_DATA_REG  0xCFC
00099 #if defined(__alpha__) || defined(__sparc__)
00100 #define PCI_EN 0x00000000
00101 #else
00102 #define PCI_EN 0x80000000
00103 #endif
00104 #define MAX_DEV_PER_VENDOR_CFG1  32
00105 #define BRIDGE_CLASS(x) (x == 0x06)
00106 #define BRIDGE_PCI_CLASS(x) (x == 0x04)
00107 #define BRIDGE_HOST_CLASS(x) (x == 0x00)
00108 #define PCI_CLASS_PREHISTORIC 0x00
00109 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
00110 #define PCI_CLASS_DISPLAY 0x03
00111 #define PCI_SUBCLASS_DISPLAY_VGA 0x00
00112 #define PCI_SUBCLASS_DISPLAY_XGA 0x01
00113 #define PCI_SUBCLASS_DISPLAY_MISC 0x80
00114 #define VIDEO_CLASS(b,s) \
00115         (((b) == PCI_CLASS_PREHISTORIC && (s) == PCI_SUBCLASS_PREHISTORIC_VGA) || \
00116          ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_VGA) ||\
00117          ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_XGA) ||\
00118          ((b) == PCI_CLASS_DISPLAY && (s) == PCI_SUBCLASS_DISPLAY_MISC))
00119 #define PCI_MULTIFUNC_DEV  0x80
00120 #define MAX_PCI_DEVICES   64
00121 #define PCI_MAXBUS 16
00122 #define PCI_IS_MEM 0x00000001
00123 #define MAX_PCI_ROM_SIZE (1024 * 1024 * 16)
00124 
00125 #define IS_MEM32(x) ((x & 0x7) == 0 && x != 0)
00126 #define IS_MEM64(x) ((x & 0x7) == 0x4)
00127 #endif